1. Field of the Invention
The present invention relates to a voltage boosting circuit in dynamic random access memory (DRAM). More particularly, the present invention relates to a voltage boosting circuit having an asymmetric metal oxide semiconductor (MOS) in DRAM.
2. Description of the Related Art
A voltage boosting circuit is required to enhance the performance of an integrated circuit that uses a low voltage to reduce power consumption. The voltage boosting circuit generates a voltage higher than the voltage supplied to integrated circuit. For example, in a DRAM, a word line voltage boosting circuit is usually used to generate a voltage signal higher than the voltage supply of the DRAM. The generated voltage is supplied to the word line of a memory to improve the read/write reliability of memory arrays in DRAM.
FIG. 1 is a circuit diagram of a conventional voltage boosting circuit. FIG. 2 is a timing diagram of the voltage boosting circuit shown in FIG. 1.
Referring to FIG. 1, a gate of an N-type MOS (NMOS) 10 connects to a voltage source 18, a source region of the NMOS 10 connects to both a row decoder 22 and a source region of an NMOS 14, and a drain region of the NMOS 10 connects to a gate of an NMOS 12. The row decoder 22 receives an address signal A.sub.i and outputs a decoded word line signal .phi..sub.s. A drain region of the NMOS 12 connects to both a column decoder 24 and a gate of the NMOS 14, and a source region of the NMOS 12 connects to a drain region of the NMOS 14, a drain region of an NMOS 16 and a word line (not shown). The column decoder 24 receives an address signal A.sub.j, and outputs a word line signal .phi.Xi and a complementary word line signal .phi.Xi. The word line signal .phi.Xi is a boosting signal and a voltage V.sub.pp of the word line signal .phi.Xi is higher than a voltage V.sub.cc of the voltage source 18. A gate of the NMOS 16 connects to the column decoder 24, and a source region of the NMOS 24 connects to a ground terminal 20.
Referring to FIGS. 1 and 2, the column decoder 24 outputs a word line signal .phi.Xi set to Low and a complementary word line signal .phi.Xi set to High. By the signals, the NMOS 14 is OFF and the NMOS 16 is ON, so that a voltage of a node N3 is equal to a voltage V.sub.ss of the ground terminal 20. Then, the row decoder 22 outputs a decoded word line signal .phi..sub.s set to High, wherein a voltage of the decoded word line signal .phi..sub.s is V.sub.cc. As a result, a voltage of a node N1 is V.sub.cc, and a voltage of a node N2 is V.sub.cc -V.sub.th1 where V.sub.th1 is a threshold voltage of the NMOS 10.
The voltage of the word line signal .phi.Xi is then set to V.sub.pp, and the difference between the voltage V.sub.pp and the voltage of a node N1 is V.sub.th2, where V.sub.th2 is a threshold voltage of the NMOS 12. Based on the above condition, the NMOS 14 is ON and the NMOS 16 is OFF, and thus, a voltage of a node N4 is V.sub.pp. When the NMOS 14 is ON, the voltage of the node N3 is equal to the voltage of the node N1. As a result, when the node N4 receives the word line signal .phi.Xi whose voltage is V.sub.pp, the voltage of the node N2 is boosted to V.sub.cc -V.sub.th1 +.alpha.V.sub.pp, in which .alpha. is a self-boosting ratio.
The design of the voltage boosting circuit described above is complex and assembled from several metal oxide semiconductors. Furthermore, an area occupied by the voltage boosting circuit is large.